1. Field of the Invention
The present invention relates to an apparatus and method for fabricating semiconductor devices, and more particularly for forming a protective step which can prevent an edge of a semiconductor wafer from being over-polished during a chemical-mechanical polishing (CMP) process.
2. Description of the Prior Art
In general, a CMP process has been applied as a planarization process for insulation layers as well as a damascene process for metallic layers.
The CMP process is employed in polishing a semiconductor wafer surface by using the friction between slurry and a pad, in which various consumables, such as slurry, a pad; a backing film, a diamond conditioner, etc., are used. The polishing property of this process is dependent upon pressure distribution between the pad and the wafer while the wafer is polished in close contact with the pad.
When the amount of polishing on one surface of a blanket wafer is uniformly maintained, pressure on the other surface of the wafer may be controlled. When the amount of polishing on an edge of the wafer is controlled, pressure on a retainer ring on the circumference of the CMP equipment may be controlled. However, there is a problem in that it is difficult to control the level of polishing resulting from a chip layout, a pattern density, a pattern height and so forth.
Before such a CMP process is performed, the wafer undergoes deposition of various thin layers, and then a predetermined pattern is formed on the wafer by photolithography and etching processes.
In the photolithography process, to inhibit photoresist contamination as well as particle generation, the photoresist applied on the wafer, in particular on the edge of the wafer, is subjected to rinsing.
The photolithography and etching processes will be specifically described below with reference to attached drawings.
Referring to FIG. 1A, to form a pattern prior to the CMP process, various thin layers are deposited on the wafer 10, and then the resulting wafer is subjected to photolithography as well as etching processes so as to form a predetermined pattern thereon.
Specifically, in the photolithography process, a predetermined insulation layer is deposited on the wafer 10, an anti-reflection layer and a photoresist layer are in turn applied on the insulation layer, an edge 12 of the wafer is rinsed, only photoresist on the edge 12 is removed, the remnant photoresist is photosensed in the presence of a mask, and a predetermined pattern 11 is formed by a reactive ion etching (RIE) process.
In general, in the RIE process, the wafer is wholly exposed to reactive gas, thereby a pattern area free from photoresist is etched together with the edge 12 of the wafer from which photoresist was rinsed and removed. Therefore, a height difference is formed in proportion to the etched amount.
In the CMP process after the thin layers are deposited on the pattern 11 which is generated by the RIE process, the edge 12 from which a part of photoresist was rinsed and removed is over-polished, which incurs damage of the wafer 10 as shown in FIG. 1B.
To avoid this problem, a dummy chip has been used, but it acts as a factor which decreases the yield of semiconductor devices. In addition, when the photoresist is not rinsed, the edge of the wafer may be free from damage. However, the wafer may not only be contaminated by the non-rinsed photoresist during transporting of the wafer. The edge thereof may be formed with particles.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide an apparatus for fabricating semiconductor devices, in which during an etching process an edge of a semiconductor wafer is constrained from being etched by using a clamp.
Another object of the present invention is to provide an apparatus for fabricating semiconductor devices, in which during an etching process an edge of a semiconductor wafer is constrained from being etched by using a shadow ring.
Another additional object of the present invention is to provide a method for fabricating semiconductor devices, in which during a CMP process after formation of a protective step on an edge of a semiconductor wafer, over-polishing, which results in a height difference between the edge and a pattern of the wafer, is prevented.
In order to accomplish these objects, according to one embodiment of the present invention, there is provided an apparatus for fabricating semiconductor devices, comprising: a wafer chuck for holding a semiconductor wafer on which various thin layers has been deposited; a processing chamber for injecting etching gas toward the wafer to form a predetermined pattern; and a clamp, attached to an edge of the wafer being held by the wafer chuck, for preventing the edge from being etched.
According to another embodiment of the present invention, there is provided an apparatus for fabricating semiconductor devices, comprising: a wafer chuck for holding a semiconductor wafer on which various thin layers has been deposited; a processing chamber for injecting etching gas toward the wafer to form a predetermined pattern; and a shadow ring, provided in the chamber upwardly spaced apart from the wafer being held by the wafer chuck, for preventing the edge from being etched.
According to another additional embodiment of the present invention, there is provided a method for fabricating semiconductor devices using a semiconductor wafer formed with various thin layers thereon, comprising the steps of: covering the thin layers with photoresist and then partially removing the photoresist from an edge of the wafer; etching the wafer except for the edge which is free from the photoresist with etching gas, so as to form a predetermined pattern; forming a protective step on the edge at the same time as the pattern is being formed; and performing planarization of the wafer formed with the pattern and the protective step.